As is well known, most of semiconductor memory devices including DRAM have a hierarchical I/O bus structure. In other words, those devices have a structure that connects global data bus GIO plural banks share to local data bus LIO prepared in each bank hierarchically.
Specifically, the global data bus is coupled with an I/O pad and the local data bus of each bank. In this structure, data transmission unit is needed for data transmission between the global data bus and the local data bus. In general, such data transmission unit comprises a write driver for driving input data on the global data bus onto the local data bus, and an I/O sense amp for loading output data on the local data bus onto the global data bus.
Meanwhile, as a size of the semiconductor memory chip becomes small, a line interval between the global data bus GIO lines (conventionally, DRAM has 16 bus lines) becomes decrease. Thus, signals on adjacent global data bus lines may be affected by noises due to coupling, resulting in an issuance of data errors under the serious state.
FIG. 1 depicts an arrangement method of a global data bus GIO in a 512M DDR2 DRAM according to the prior art.
As shown in FIG. 1, a memory device comprises 4 banks, BANK0 to BANK3. Each bank includes even cell region and odd cell region. And, the even cell region and the odd cell region share one row decoder XDEC, each of which is unit region selected by separate column decoder YDEC. Each of the even cell region and the odd cell region is provided with local data bus LIO and also data transmission unit, independently.
In the meantime, there are arranged 16 I/O pads DQ between upper banks BANK0 and BANK1 and lower banks BANK2 and BANK3, and also is arranged global data bus GIO in a row direction between the I/O pads DQ and the upper banks BANK0 and BANK1. Also, there is arranged a global data bus GIO (not shown) between the I/O pads DQ and the lower banks BANK2 and BANK3. For reference, the bus line in a row direction (or horizontal direction) is embodied in a first metal wire, and the bus line in a column direction (or vertical direction) is implemented with a second metal wire, in which the first and the second metal wires are coupled via a contact.
The global data bus GIO has 16 bus lines corresponding to the 16 I/O pads DQ, wherein adjacent two banks BANK0 and BANK1 hold those bus lines in common. To be more specific, each of the 16 data transmission units corresponding to the local data buses LIOs in the odd cell regions of each of the banks BANK0 and BANK1 shares one global data bus line. Likewise, each of the 16 data transmission units corresponding to the local data buses LIOs in the even cell regions of each of the banks BANK0 and BANK1 shares one global data bus line. Accordingly, there are arranged total 32 global data bus lines between the I/O pads DQ and the upper banks BANK0 and BANK1.
For information, it is known that the layout order, 0, 15, 1, 14, 2, 13, 3, 12, 4, 11, 5, 10, 6, 9, 7, 8, of the I/O pads DQ and the data transmission units is an unique sequence according to pin configuration under the standard specification.
In the prior art arraying the bus lines of the global data bus, as described above, the 16 global data bus lines for connection between the odd cell regions of the two banks BANK0 and BANK1 and the I/O pads DQ are arrayed in the order of 0, 15, 1, 14, 2, 13, 3, 12, 4, 11, 5, 10, 6, 9, 7, 8, based on the layout sequence of the I/O pads DQ and the data transmission units; and following the above sequence, the 16 global data bus lines for connection between odd cell regions of the two banks BANK0 and BANK1 and the I/O pads DQ are arrayed in sequence.
According to this global data bus GIO arrangement method, there occurs constant overlap interval (for the interval embodied in the first metal wire merely) between the adjacent global data bus lines. This overlap interval may be a primary factor that originates coupling noise in the adjacent global data bus lines as mentioned above, wherein it is shown in the general sequential global data bus GIO arrangement method that the overlap interval is maximum, meaning an issuance of maximum coupling noise.
In case of the existing memory chip, such coupling noise between the bus lines is not an issue since layout area for routing of the global data bus is fully guaranteed. However, as the memory chip becomes high integrated, the enlargement of the bank region is inevitable and thus the layout area for routing of the global data bus becomes relatively small. Accordingly, this coupling noise between the adjacent global data bus lines has been very important consideration in the process of the chip design. Meanwhile, since it is expected that the future memory chip supports more wide bandwidth and is provided with the global data bus of 32 or 64 bits, it will be apparent that the coupling noise between the adjacent global data bus lines would occur more serious problem.
As one scheme of alleviating this coupling noise, there may be a guarantee of the space between the global data buses, which may not be a consideration due to a shortcoming that increases the chip size.
As another scheme, meanwhile, there may be an idea that makes the layout sequence of the global data bus lines random, contrary to the concept that arraying the global data lines sequentially results in maximum coupling noise. In this case, the total coupling noise amount of the global data bus may decrease compared to the existing method shown in FIG. 1, but makes a length of the overlap interval for each line inconstant. As such, if the length of the overlap interval for each line is not constant, then the loading value of each global data bus line is different. This may result in a problem allowing a different delay time for each line. In this case, there may be a need of an extra circuit for removing skew between the global data bus lines, and also may be a difficulty to guarantee the chip's operation characteristics since the skew by lines is also random although the skew circuit is utilized while yielding damage to the chip area.